Closed-loop clock circuits, such as phase-locked and delay-locked loops, are useful in many applications, including clock and data recovery, data retiming, clock regeneration, and other functions. Delay-locked loops are particularly useful in high-speed systems such as high-speed memory systems.
Delay-locked loops can generate clock signals, or they can receive clocks signals. For example, a delay-locked loop in a first circuit may generate and provide a clock signal to a delay-locked loop in a second circuit. These delay-locked loops can clean up clock signals by removing jitter and spurious noise components. They can also retime signals to improve the performance of data transfer systems.
The duty cycle of these clock signals may become corrupted. For example, driver pull-up and pull-down capabilities may be mismatched. That is, a driver may pull a voltage on a bus line low faster than the driver can pull it high. This in turn causes skew between clock rising and falling edges. Also, coupling from other signals may speed up one edge or slow another edge, again causing skew between clock edges. Trace capacitance may slow rising and falling edges of a clock signal received by an input buffer or other circuit. If the switch point of the receiving circuit is not centered, the recovered clock signal may have duty-cycle errors.
These duty-cycle errors add to any jitter component in the clock signal. As such, edges of the clock signal may not be centered on received data. Accordingly, these clock duty-cycle errors may degrade data transmission and increase data transfer error rates.
Closed-loop clock circuits by themselves typically cannot improve a clock signal duty cycle. While they are capable of removing transitory jitter, they are not capable of removing static errors in a duty-cycle distortion. Accordingly, additional circuitry may be used.
Thus, what is needed are circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals received by or generated by closed-loop clock circuits, such as phase-locked and delay-locked loops.